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HFA3841
TM
P RE L I M I NA R Y
Data Sheet
January 2000
File Number
4661.2
Wireless LAN Medium Access Controller
The Intersil HFA3841 Wireless LAN Medium Access Controller is part of the PRISM(R) Enterprise 2.4GHz WLAN chip set. The HFA3841 directly interfaces with the Intersil HFA386x family of Baseband Processors, offering a complete end-toend chip set solution for wireless LAN products. Protocol and PHY support are implemented in firmware to allow custom protocol and different PHY transceivers. The HFA3841 is designed to provide maximum performance with minimum power consumption. External pin layout is organized to provide optimal PC board layout to all user interfaces. Firmware implements the full IEEE 802.11 Wireless LAN MAC protocol. It supports BSS and IBSS operation under DCF, and operation under the optional Point Coordination Function (PCF). Low level protocol functions such as RTS/CTS generation and acknowledgement, fragmentation and de-fragmentation, and automatic beacon monitoring are handed without host intervention. Active scanning is performed autonomously once initiated by host command. Host interface command and status handshakes allow concurrent operations from multi-threaded I/O drivers. Additional firmware functions specific to access point applications are also available. Designing wireless protocol systems using the HFA3841 is made easier with the availability of evaluation board, firmware, software device drivers, and complete documentation.
Features
* IEEE802.11 Standard Data Rates: 1, 2, 5.5 and 11Mbps * Part of the Intersil PRISM Wireless LAN Chip Set * Full Implementation of the MAC Protocol Specified in IEEE Std. 802.11-1999 and the 802.11b Draft Standard * Host Interface Supports Full 16-Bit Implementation of PC Card 95, also ISA PnP with Additional Chip * Host Interface Provides Dual Buffer Access Paths * External Memory Interface Supports up to 4M bytes RAM * Internal Encryption Engine Executes IEEE802.11 WEP * Low Power Operation; 25mA Active, 8mA Doze, <1mA Sleep * Operation at 2.7V to 3.6V Supply * 3V to 5V Tolerant Input/Outputs * 128 Pin LQFP Package Targeted for Type II PC Cards * IEEE802.11 Wireless LAN MAC Protocol Firmware and Microsoft(R) Windows(R) Software Drivers
Applications
* High Data Rate Wireless LAN * PC Card Wireless LAN Adapters * ISA, ISA PnP WLAN Cards * PCI Wireless LAN Cards (Using Ext. Bridge Chip) * Wireless LAN Modules * Wireless LAN Access Points * Wireless Bridge Products * Wireless Point-to-Multipoint Systems
Ordering Information
PART NUMBER HFA3841CN HFA3841CN96 TEMP. RANGE (oC) 0 to 70 0 to 70 PACKAGE 128 Ld LQFP Tape and Reel PKG. NO. Q128.14x20
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
Microsoft(R) and Windows(R) are registered trademarks of Microsoft Corporation. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000 PRISM(R) is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.
Preliminary - HFA3841 Pinout
HREGHD0 HD1 HD2 VCC_IO3 VSS_IO3 HD8 HD9 HD10 PL7 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10 VCC_IO3 VSS_IO3 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 NVCSVSS_IO3 VCC_IO3
MA1
MA0
MWELMOERAMCS-
102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
PJ4
HCE1HD7 HD6 HD5 HD4 HD3 PJ6 PJ5 PJ7 TCLKIN PL6 PL5 VSS_CORE3 VCC_CORE3 PL0 RESET TXD TXC RXD RXC PK5 PK6 PK7 VSS_CORE3 VCC_CORE3 PL2 PL1 PL3 PJ3 PJ1 PJ0 PJ2 PK2 PK1 PK0 HSTSCHGVSS_CORE3
Simplified Block Diagram
PRISM RADIO BASEBAND PROCESSOR TXD/RXD CTRL/STATUS SERIAL CONTROL
HFA3841
MICROPROGRAMMED MAC ENGINE PC CARD HOST INTERFACE
HOST COMPUTER
PHY INTERFACE (MDI) WEP ENGINE
DATA ADDRESS CONTROL
PRISM RADIO RF SECTION
SERIAL CONTROL (MMI)
MEMORY CONTROLLER
ON-CHIP MEMORY
RADIO AND SYNTH SERIAL CONTROL ADDRESS 44MHz CLOCK SOURCE EXTERNAL SRAM AND FLASH MEMORY SELECT DATA
2
CLKOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
HINPACKHWAITVCC _IO5 HA0 HA1 HA2 HA3 HA4 HA5 HA6 HA7 HIREQVSS _IO3 HWEHA8 HA9 HIOWRHIORDHOEHCE2HD15 VCC _IO3 HD14 HD13 HD12 HD11
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
INDEX
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
PK4 PK3 TRSTMD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 VCC_CORE3 VSS_IO3 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 PL4 VSS_IO3 XTALO XTALI VCC_CORE3
Preliminary - HFA3841 HFA3841 Pin Descriptions
Host Interface Pins
PIN NAME HA0-9 HCE1HCE2HD0-15 PIN NUMBER PIN I/O TYPE DESCRIPTION PC Card address input, bits 0 to 9 PC Card card select, low byte PC Card card select, high byte PC Card data bus, bit 0 to 15
106-113, 117, 118 5V tol, CMOS, Input, 50K Pull Down 1 122 101-99, 6-2, 96-94, 128-125, 123 103 120 119 114 5V tol, CMOS, Input, 50K Pull Up 5V tol, CMOS, Input, 50K Pull Up 5V tol, BiDir, 2mA, 50K Pull Down
HINPACKHIORDHIOWRHRDY/HIREQ-
CMOS Output, 2mA 5V tol, CMOS, Input, 50K Pull Up 5V tol, CMOS, Input, 50K Pull Up CMOS Output, 4mA
PC Card I/O decode confirmation PC Card I/O space read PC Card I/O space write PC Card interrupt request (I/O mode) Card ready (memory mode) PC Card memory attribute space output enable PC Card attribute space select
HOEHREGHRESET
121 102 16
5V tol, CMOS, Input, 50K Pull Up 5V tol, CMOS, Input, 50K Pull Up 5V tol, CMOS, ST Input, 50K Pull Up Hardware Reset CMOS Output, 4mA CMOS Output, 4mA 5V tol, CMOS Input, 50K Pull Up
HSTSCHGHWAITHWE-
36 104 116
PC Card status change PC Card not ready (force host wait state) PC Card memory attribute space write enable
Memory Interface Pins
PIN NAME MA0 MWEHPIN NUMBER 72 PIN I/O TYPE CMOS TS Output, 2mA DESCRIPTION MBUS address bit 0 (byte) for x8 memory High byte write enable for x16 memory MBUS address bits 1 to 18 MBUS address bit 19 MBUS address bit 20 MBUS address bit 21 Memory output enable Low (or only) byte memory write enable RAM select NV memory select MBUS low data byte, bits 0 to 7 MBUS high data byte, bits 8 to 15
MA1-18 PL4 PL5 PL6 MOEMWELRAMCSNVCSMD0-7 MD8-15
73-81, 84-92 43 12 11 70 71 69 68 61-54 51-44
CMOS TS Output, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA, 50K Pull Up CMOS BiDir, 2mA CMOS TS Output, 2mA CMOS TS Output, 2mA CMOS TS Output, 2mA CMOS TS Output, 2mA 5V tol, CMOS, BiDir, 2mA, 100K Pull Up 5V tol, CMOS, BiDir, 2mA 50K Pull Down
3
Preliminary - HFA3841
Radio Interface and General Purpose Port Pins
PIN NAME TXD TXC RXD RXC PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 PIN NUMBER 17 18 19 20 31 30 32 29 65 8 7 9 35 34 33 63 64 21 22 23 15 27 26 28 43 12 11 93 PIN I/O TYPE CMOS Output, 2mA, 50K Pull Down 5V tol, CMOS, BiDir 2mA, ST CMOS Input CMOS Input, ST CMOS BiDir, 2mA, ST, 50K Pull Down CMOS BiDir, 2mA, 50K Pull Down CMOS BiDir, 2mA, 50K Pull Down CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA, 50K Pull Up CMOS BiDir, 2mA CMOS BiDir, 2mA, 50K Pull Up CMOS BiDir, 2mA, ST, 50K Pull Down CMOS BiDir, 2mA, 50K Pull Down CMOS BiDir, 2mA, 50K Pull Down CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA, 50K Pull Up MBUS address bit 20 CMOS BiDir, 2mA CMOS BiDir, 2mA MBUS address bit 21 or PHY control I/O Transmitter ready MBUS address bit 19 Transmitter enable Receiver enable (or PHY sleep control) MDREADY - PHY or MAC data available (in) Medium busy (CCA from PHY) DESCRIPTION OF FUNCTION (IF OTHER THAN IO PORT) Transmit data out Transmit clock in/out Receive data in Receive clock in MMI serial clock in/out MMI serial data in/out MMI serial data read/write control, or data output MMI device enable
Clocks
PIN NAME XTALI XTALO CLKOUT TCLKIN PIN NUMBER 40 41 38 10 CMOS Input, ST CMOS Output, 2mA CMOS, TS Output, 2mA CMOS Input, ST, 50K Pull Down PIN I/O TYPE DESCRIPTION Crystal or external clock input (at >= 2X desired MCLK frequency) Crystal output Clock output (selectable as OSC or MCLK) Timebase Reference Clock Input
4
Preliminary - HFA3841
Power
PIN NAME VCC_CORE3 VCC_IO3 VCC_IO5 VSS_CORE3 VSS_IO3 TRSTPIN NUMBER 14, 25, 39, 53 66, 83, 98. 124 105 13, 24, 37 42, 52, 67, 82, 97, 115 62 PIN I/O TYPE 3.3V Core Supply 3.3V I/O Supply 5V Tolerance Supply Core VSS I/O VSS CMOS Input Reserved - Must be tied low through 1K DESCRIPTION
ST = Schmitt Trigger (Hysteresis), TS = Three-State. Signals ending with "-" are active low. NOTE: Output pins typically drive to positive voltage rail less 0.1V. Hence with a supply of 2.7V the output will just meet 5V TTL signal levels at rated loads.
Port Pin Uses for PRISM Application
PIN 20 19 18 17 31 30 32 NAME RXC RXD TXC TXD PJ0 PJ1 PJ2 PRISM I USE RXC - Receive clock RXD - Receive data TXC - Transmit clock TXD - Transmit data SCLK - Clock for the SD serial bus. SD - Serial bi-directional data bus R/W - An input to the HFA3860A used to change the direction of the SD bus when reading or writing data on the SD bus. PRISM IITM USE RXC - Receive clock RXD - Receive data TXC - Transmit clock TXD - Transmit data SCLK - Clock for the SD serial bus. SD - Serial bi-directional data bus Not Used
29 65 8
PJ3 PJ4 PJ5
CS - A Chip select for the device to activate the se- CS_BAR - Chip select for HFA3861 baseband rial control port. (active low) (active low) Not Used PE1 - Power Enable 1
SYNTH_LE - Latches a frame of 22 bits after it has LE_IF - Load enable for HFA3783 Quad IF been shifted by the SCLK into the synthesizer registers. LED - Activity indicator Not Used Not Used Not Used Not Used TX_PE_RF - Power Enable RX_PE_RF - Power Enable LED - Activity indicator RADIO_PE - RF power enable LE_RF - Load enable for HFA3983 RF chip SYNTHCLK - Serial clock to front end chips SYNTHDATA - Serial data to front end chips PA_PE - Transmit PA power enable PE2 - Power Enable 2
7 9 35 34 33 63 64 21 22 23 15 27 26 28 43 12 11 93
PJ6 PJ7 PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7
MD_RDY - Header data and data packet are ready MDREADY - Header data and data packet are to be transferred from Baseband on RXD ready to be transferred from Baseband on RXD CCA - Signal that the channel is clear to transmit. RADIO_PE - Master power control for the RF section CCA - Signal that the channel is clear to transmit. CAL_EN - Calibration mode enable
TX_PE and PA_PE - Transmit Enable to Baseband TX_PE - Transmit Enable to Baseband RX_PE - Receive Enable to Baseband RESET - Reset to Baseband Not Used MA19 (if required) MA20 (if required) MA21 (if required) RX_PE - Receive Enable to Baseband RESET_BB - Reset Baseband T/R-SW_BAR - Transient/Receive Control (Inverted) MA19 (if required) MA20 (if required) Reserved
TX_RDY - Baseband ready to receive data on TXD T/R_SW - Transmit/Receive Control (not used by firmware)
5
Preliminary - HFA3841
Special Hardware Functions for Port Pins
PJ0 PJ1 PJ2 PJ3 SCK SDO/SDIO MOSI SDI/MISO SDDIR SDE0 PCSPHYCSPJ4 SDE1 SDDQ SSPJ5 PJ6 PJ7 PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 MREQMGNTLED2 LED1 GPCK UHSIn GPDO UTXD GPDI URXD GPDS0 UHSOut GPDS1 PDA UWDET MBUSY RATE0 EDET RATE1 TXE RXE PHYSLP PHYRES SLOT ANTSEL MA19 LED0 MA20 MA21 TXR MMI serial clock in or out MMI serial data out or I/O SPI Master Out/Slave In MMI serial data in MMI (SDIO) data direction MMI serial device enable 0 SPI/MMI transfer qualifier PHY chip select (3-3.5MB) MMI serial device enable 1 MMI data delivery qualifier SPI slave select MBUS request MBUS grant LED 2 driver LED 1 driver GP serial port clock in or out Async handshake in GP serial port data output Async transmit data GP serial port data input Async receive data GP device select 0 Async handshake out GP device select 1 PHY (or MAC) data available Unique word detected Medium busy Data Rate select 0 Energy (or modulation) detect Data Rate select 1 Transmitter enable Receiver enable PHY sleep PHY reset Slot time reference (in or out) Antenna select MBUS address bit 19 LED 0 driver MBUS address bit 20 MBUS address bit 21 Transmitter ready (Directly from I/O port) For 1M byte SRAM (Directly from I/O port) For 2M byte SRAM For 4M byte SRAM Can drive "awake" LED (Directly from I/O port) (Directly from I/O port) Qualifies RXD input to MAC controller Output from MAC controller CCA status (PHY-dependent source) Indicates GP port async Rx ready Indicates external async Rx ready (Directly from I/O port) (Directly from I/O port) Also for MicroWire Or SPI Master In/Slave Out Low while SDIO is driven as an output Generally selects PHY controller Asserted by hardware during transfer For memory-mapped PHY controllers For serial EPROM, synthesizer, etc. Low for data on SDIO, high for address In slave mode SCK is serial clock input
6
Preliminary - HFA3841
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .100oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only)
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.70V to +3.60V Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER Power Supply Current Standby Power Supply Current Input Leakage Current Output Leakage Current Logical One Input Voltage Logical Zero Input Voltage Logical One Output Voltage Logical Zero Output Voltage Input Capacitance Output Capacitance
Maximum test temperature = 100oC, VCC = 3.0V to 3.3V 10%, TA = -40oC to 85oC SYMBOL ICCOP ICCSB II IO VIH VIL VOH VOL CIN COUT TEST CONDITIONS VCC = 3.6V, CLK Frequency 44MHz VCC = Max, Outputs not Loaded VCC = Max, Input = 0V or VCC VCC = Max, Input = 0V or VCC VCC = Max, Min VCC = Min, Max IOH = -1mA, VCC = Min IOL = 2mA, VCC = Min CLK Frequency 1MHz. All measurements referenced to GND. TA = 25oC CLK Frequency 1MHz. All measurements referenced to GND. TA = 25oC MIN -10 -10 0.7VCC VCC-0.2 TYP 35 0.5 1 1 0.2 5 5 MAX 45 1 10 10 VCC/3 0.2 10 10 UNITS mA mA mA mA V V V V pF pF
NOTE: All values in this table have not been measured and are only estimates of the performance at this time.
AC Electrical Specifications
PARAMETER CLOCK SIGNAL TIMING OSC Clock Period (Typ. 44MHz) High Period Low Period Delay from OSC Edge to MCLK Edge EXTERNAL MEMORY INTERFACE Rising Edge MCLK to EMA[15:0], EMCSxN, EMOEN, EMWRN Width EMOEN EMD[15:0] Read Data Setup EMD[15:0] Read Data Hold Minimum Width between Read and Write Width EMWRN EMWRN Rising to EMCSxN Rising EMD[15:0] Write Data Hold Time to Rising Edge EMWRN tD1 tD2 tS1 tH1 tD3 tD4 tD5 tD6 0 2*tMCLK - 10 10 tMCLK - 10 2*tMCLK - 10 1*tMCLK - 10 1*tMCLK - 10 tMCLK 1*tMCLK 1*tMCLK 10 9*tMCLK + 10 0 tMCLK + 10 9*tMCLK + 10 1*tMCLK + 10 1*tMCLK + 10 ns ns ns ns ns ns ns ns tCYC tH1 tL1 tD1 22 15 15 22.7 11.36 11.36 10 200 SYMBOL MIN TYP MAX UNITS
7
Preliminary - HFA3841
AC Electrical Specifications
SYNTHESIZER SPCLK Period SPCLK Width Hi SPCLK Width Lo SYNCLE to Rising Edge SPCLK SPDATA Hold Time from Falling Edge of SPCLK SPCLK Falling Edge to SYNLE Inactive SERIAL PORT - HFA3824A/HFA3860B SPCLK Clock Period High Period Delay from Clock Falling Edge to SPCSx, SPAS, SPREAD, SPDATA Outputs Setup Time of SPDATA Read to SPCLK Falling Edge Hold Time of SPDATA Read from SPCLK Falling Edge Hold Time of SPDATA Write from SPCLK Falling Edge SYSTEM INTERFACE - PC CARD IO READ 16 Data Delay After SIORDN Data Hold Following SIORDN SIORDN Width Time Address Setup Before SIORDN SCE(1,2)N Setup Before SIORDN SCE(1,2)N Hold After SIORDN SREGN Setup Before SIORDN SREGN Hold Following SIORDN SINPACKN Delay Falling from SIORDN SINPACKN Delay Rising from SIORDN SIOIS16N Delay Falling from Address SIOIS16N Delay Rising from Address SWAITN Data Delay from SWAITN Rising SWAITN Width Time SYSTEM INTERFACE - PC CARD IO WRITE 16 Data Setup Before SIOWRN Data Hold Following SIOWRN SIOWRN Width Time Address Setup Before SIOWRN Address Hold Following SIOWRN SCE(1,2)N Setup Before SIOWRN SCE(1,2)N Hold Following SIOWRN SREGN Setup Before SIOWRN SREGN Hold Following SIOWRN tSUIOWR tHIOWR tWIOWR tSUA tHA tSUCE tHCE tSUREG tHREG 60 30 165 70 20 5 20 5 0 ns ns ns ns ns ns ns ns ns tDIORD tHIORD tWIORD tSUA tSUCE tHCE tSUREG tHREG tDFINPACK dDRINPACK tDFIOIS16 tDRIOIS16 tDFWT tDRWT tWWT 0 165 70 5 20 5 0 0 100 45 45 35 35 35 0 12,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCYC tH1, tL1 tCD tDRS tDRH tDWH 90ns tCYC/2 -10 15 0 0 10 4s tCYC/2 + 10 ns ns tCYC tH1 tL1 tD1 tD2 tD3 90 tCYC /2 - 10 tCYC /2 - 10 35 0 35 4,000 tCYC /2 + 10 tCYC /2 + 10 ns ns ns ns ns ns (Continued) SYMBOL MIN TYP MAX UNITS
PARAMETER
8
Preliminary - HFA3841
AC Electrical Specifications
SIOIS16N Delay Falling from Address SIOIS16N Delay Rising from Address SWAITN Delay Falling from IOWRN SWAITN Width Time SIOWRN High from SWAITN High RADIO TX DATA - TX PATH TXC Rising to TXD TXC Period TXC Width Hi TXC Width Lo MCLK Period TXC Rising to TX_PE2 Deassert (See Note 9) TX_RDY Assert Before TXC Rising TX_RDY Hold After TXC Rising (See Note 2) RADIO RX DATA - RX PATH RX_RDY Setup Time to RXC Positive Edge (See Note 3) RX_RDY Hold Time from RXC Positive Edge (See Note 4) RX_PE2 Delay from RX_RDY deAssert (See Note 8) RX_PE2 Low Pulse Width (See Note 7) RXD Setup Time to RXC Positive Edge (See Note 5) RXD Hold Time from RXC Positive Edge (See Note 5) RXC Period (See Note 9) MCLK Period RXC Width Hi RXC Width Lo NOTES: 2. TX_RDY is and'd with TXC_ONE_SHOT to shift data in shift register. However, once the last data bit is put on TXD output pin no further shifting of bits is required. In addition, TX_RDY remains asserted until TX_PE2 is de-asserted which occurs several MAC MCLK's after the last data bit is shifted into the BBP TX_PORT. Therefore, 0ns hold time is required for this signal. TX_RDY is used by the BBP to signal that the PLCP header and preamble have been generated and the MAC must provide the MPDU data. TX_RDY will remain asserted until TX_PE2 is deasserted by the MAC. TX_PE2 is async to the TX_PORT. 3. MD_RDY is and'd with RXC_ONE_SHOT (RXDAV) to shift data in shift register. RX_RDY is not required to be valid until 1 MCLK after RXC is sampled high. Therefore, a negative setup time could be used. Since this is an unlikely scenario, we will leave it at a nominal 10ns setup time. 4. MD_RDY is and'd with RXC_ONE_SHOT (RXDAV) to shift data in shift register. Therefore, for the last data bit, the MD_RDY must be held active until RXC_ONE_SHOT is sampled high by MAC's MCLK. However, it is assumed that BBP will be used in a mode that keeps RX_RDY (MD_RDY) and RXC running until RX_PE2 is de-asserted. The MAC will stop processing data after the number of bits retrieved from the PLCP header length field are received. THEREFORE, the RX_RDY hold time with respect to RXC does not matter. However, should the RX_RDY signal be cleared when the last RXD bit is received the hold time w/r RXC must be honored. 5. RXC positive edge clocks a flop which stores the RXD for internal usage. 6. RXC period (and Hi/Lo times) must be long enough for flops clocked by MAC MCLK to see 1 RXC high and 1 RXC low. Since RXC can be async to MAC MCLK it is assumed that 3 MCLK periods will suffice. 7. RX_PE inactive width at BBP is 3 BBP MCLK's. Since BBP MCLK and MAC MCLK can be async minimum should be 4 MAC MCLK's. 8. Not yet verified, but seems reasonable. When RX_RDY drops before expected number of RXD bits is received, then Tx/Rx FSM in mpctl.v signals timers which clear rx_pe2_int. More of a functional spec than a timing spec. 9. Need to sample 1 RXC high and 1 RXC low with MAC MCLK. tSURX_RDY tHRX_RDY tDRX_PE2 tWRX_PE2 tSURXD tHRXD tRXC tMCLK tRCHM tRCLM 10 45 10 0 22.7 31 31 3 * tMCLK 4 * tMCLK 3 * tMCLK ns ns ns ns ns ns ns ns ns ns tDTXD tTXC tCHM tCLM ttMCK tDTX_PE2 tTX_RDY tTX_RDYH 4* tTMCK 31 31 22.7 10 0 TBD 10 TBD ns ns ns ns ns ns ns (Continued) SYMBOL tDFIOIS16 tDRIOIS16 tDFWT tWWT tDRIOWR MIN 0 TYP MAX 35 35 35 12,000 UNITS ns ns ns ns ns
PARAMETER
9
Preliminary - HFA3841 Waveforms
OSC tH1 tD1 MCLK (INTERNAL) tCYC tH1
FIGURE 1. CLOCK SIGNAL TIMING
44MHz 23ns OSC 10ns (NOTE 10) 11MHz 91ns MCLK (INTERNAL) QCLK (INTERNAL) 23ns MCLKOUT 11.5ns ADDRESS, RAMCS_ 17ns MOE_ 24ns MD0-15 READ DATA VALID DATA AT MDIN 13ns MWEH/L_ tH0 MD0-15, WRITE DATA 20ns MBUS READ CYCLE MBUS WRITE CYCLE VALID DATA 16ns tH0 17ns
NOTE: 10. Timing delays between OSC and internal clocks are shown for information purposes only. FIGURE 2. MBUS MEMORY TIMING - 11MHz MCLK
10
Preliminary - HFA3841 Waveforms (Continued)
44MHz 23ns OSC 10ns (NOTE 12) 14.67MHz 68.2ns MCLK (INTERNAL) QCLK (INTERNAL)
10ns (NOTE 12)
10ns (NOTE 12)
MCLKOUT 11.5ns ADDRESS, RAMCS_ 17ns MOE_ 24ns MD0-15 READ DATA VALID DATA AT MDIN tH0 17ns
13ns MWEH/L_
16ns
tH0 MD0-15 WRITE DATA 20ns MBUS READ CYCLE MBUS WRITE CYCLE VALID DATA
NOTES: 11. 14.67MHz requires an odd divisor in the prescaler. Note that both edges of OSC are used to create MCLK and QCLK, thus a deviation from 50% duty cycle in OSC will result in corresponding changes in MBUS timing. 12. Timing delays between OSC and internal clocks are shown for information purposes only. FIGURE 3. MBUS MEMORY TIMING - 14.67MHz MCLK
MCLK tD1 EMA [15:0] EMCSxN tD2 EMOEN tD3 EMWRN tS1 tH1 tD1 tD4 tD5
tD6
EMD [15:0]
FIGURE 4.
11
Preliminary - HFA3841 Waveforms (Continued)
SPCLK tH1 SYNLE SPCSPWR tD1 SPDATA D[n] tL1 tCYC tD2 D[n -1] D[n -2] D[2] D[1] D[0] tD3
FIGURE 5. SYNTHESIZER
SPCLK TH1 SPCSX tCYC tCD SPAS tCD TL1 tCD
tCD SPREAD (READ)
tCD
tDRS tDRH SPDATA (READ) A[7] tCD SPREAD (WRITE) tDWH SPDATA (WRITE) A[7] A[6] A[0] D[7] D[1] D[0] A[6] A[0] D[1] D[0]
tCD
FIGURE 6. SERIAL PORT - HFA3824A/HFA3860B
12
Preliminary - HFA3841 Waveforms (Continued)
SA[15:0] tSUREG SREGN ISUCE SCE(1, 2) N tWIORD tDIORD SIORDN tSUA SINPACKN tDFIOIS16 SIOIS16N tDRIOIS16 tDFINPACK tDRINPACK tHCE tHREG tHA
SWAITN tDFWT D[15:0] tWWT tDRWT tHIORD
FIGURE 7. PC CARD IO READ 16
SA[15:0] tSUREG SREGN tHCE tHREG tHA
tSUCE SCE (1, 2) N tSUA tWIOWR
SIOWRN tDFIOIS16 SIOIS16N tDRIOWR SWAITN tDFWT tSUIOWR tWWT tHIOWR tDRINPACK tDRIOIS16
D[15:0]
FIGURE 8. PC CARD IO WRITE 16
13
Preliminary - HFA3841 Waveforms (Continued)
TXDATA
TXCLK tTX_RDY TX_RDY
TX_PE2
FIGURE 9. TX PATH
TXD tDTXD TXCLK
A
B tTXCLK tCHM
C
tCLM
tMCLK
MCLK
TXCLK_INT
TXCLK_INT2
TXCLK_ONE _SHOT
TXD_INT
A
B
C
FIGURE 10.
14
Preliminary - HFA3841 Waveforms (Continued)
RXDATA
RXCLK tSURX_RDY RX_RDY tDRX_PE2 RX_PE2 tWRX_PE2 tHRX_RDY
CCA tCCAF
FIGURE 11. RX PATH
RXDATA
A
B
C
tRCHM
tSURXD
tHRXD
RXCLK tRCLM tRXCLK A B tMCLK
RXD_INT
MCLK
RXCLK_INT
RXCLK_INT2
RXCLK_ONE _SHOT
FIGURE 12.
15
Preliminary - HFA3841 HFA3841 System Overview
I/O BUS HOST SYSTEM (I/O DRIVER) HOST INTERFACE HFA3841 WIRELESS MAC CONTROLLER MAC BRIDGE FOR ACCESS POINT
FOR STATION ADAPTER
PHY TRANSCEIVER
WIRELESS MEDIUM
LAN DISTRIBUTION SYSTEM
FIGURE 13. TYPICAL APPLICATION
HFA3841 MD0..15 MA1..17 NVCS_ MOE_ MD0..7
FLASH 128Kx8
MA0..16 CS_ OE_
SPAM 128Kx8 MD0..7 MA1..17 OE_ MWEL_ MA0/MWEH_ RAMCS_ WE_ CS_ SRAM 128Kx8 MD8..15 MA1..17 OE_ WE_ CS_
FIGURE 14.
External Memory Interface
An external memory space is provided for firmware and for buffers that are used for temporary storage of received and transmitted frames. The total memory space is 4M bytes. 64K words are used for control store, where firmware is located. The high data bus has weak pull-up resistors so that external pull-down resistors can set the configuration of the HFA3841 during reset. NVCS- is the enable to the Flash memory device. Typically the contents of the Flash are copied entirely into SRAM at initialization, and then rarely if ever accessed during normal operation. For this reason, it is acceptable to use low cost, slow Flash devices. During initialization, the clock prescaler is set to produce a longer cycle time while the Flash is accessed. Once all the data has been copied, execution 16
jumps into SRAM and the clock is raised to the normal operating frequency. It is possible to operate without a Flash device. In such a system, the firmware must be downloaded through the host interface before operation can commence. The external SRAM memory must be organized in a 16-bit width to provide adequate performance to implement the 802.11 protocol at 11Mb/s rates. Systems designed for lower performance applications may be able to use 8-bit wide memory. The minimum implementation of external memory consists of 128K bytes of SRAM organized as 64K x 16. Typical applications will use 256K bytes organized as 128K x 16. An access point application could make use of the full address space of the device with 4M bytes organized as 2M x 16.
Preliminary - HFA3841
The HFA3841 was designed to implement 16-bit wide memory by using two 8-bit RAM chips. The HFA3841 provides high and low write enable signals (MWEH_ and MWEL_), and a single output enable (MOE_). This allows a direct connection, enabling a pair of 8-bit SRAMs to function as a 16-bit device. MA0 functions as Address 0 for 8-bit access (such as Flash), and as MWEH (High Byte Write Enable) for 16-bit access (such as SRAM), since address bit 0 is not used for 16-bit accesses. Some single chip 16-bit SRAMs use an alternate connection scheme with five pins: a Chip Select, an Output Enable, a single Write Enable, and Upper and Lower byte enables, which control both read and write cycles. Thus, external logic is required to generate the required signals. See Application Note AN9844, "HFA3841 to PRISMII Connections" for important information regarding the connection of these types of 16-bit SRAM chips to the HFA3841. HWE-, HOEHOE- and HWE- are only used to access attribute memory. Common Memory, as specified in the PC Card standard, is not used in the HFA3841. HOE- is the strobe that enables an attribute memory read cycle. HWE- is the corresponding strobe for the attribute memory write cycle. The attribute space contains the Card Information Structure (CIS) as well as the Function Configuration Registers (FCR). HIORD-, HIOWRHIORD- and HIOWR- are the enabling strobes for register access cycles to the HFA3841. These cycles can only be performed once the initialization procedure is complete and the HFA3841 has been put into IO mode. HREGThis signal must be asserted for I/O or attribute cycles. A cycle with HREG- unasserted will be ignored as the HFA3841 does not support common memory. HINPACKThis signal is asserted by the HFA3841 whenever a valid I/O read cycle takes place. A valid cycle is when HCE1-, HCE2-, HREG-, and HIORD- are asserted, once the initialization procedure is complete. HWAITWait states are inserted in accesses using HWAIT-. The host interface synchronizes all PC Card cycles to the internal HFA3841 clock. The following wait states should be expected: Direct Read or Write to Hardware Register * 1/2 to 1 MCLK assertion of HWAIT- for internal synchronization. Write to Memory Mapped Register, Buffer Access Path, or Attribute Space (Post-Write) * The data required for the write cycle will be latched and therefore only the synchronizing wait state will occur. * Until the queued cycle has actually written to the memory, any subsequent access by the Host will result in a WAIT. Read to Attribute Space and Memory Mapped Registers * WAIT will assert until the memory arbitration and access have completed. Buffer Access Paths, BAP0 and BAP1 * An internal Pre-Read cycle to memory is initiated by a host Buffer Read cycle, after the internal address pointer has auto-incremented. If the next host cycle is a read to the same buffer, the data will be available without a memory arbitration delay. * A single register holds the pre-read data. Thus, any read access to any other memory-mapped register (or the other
Host Interface
PC Card Physical Interface
The Host interface is compatible to the PC Card 95 Standard (PCMCIA v2.1). The HFA3841 Host Interface pins connect directly to the correspondingly named pins on the PC Card connector with no external components (other than resistors) required. The HFA3841 operates as an I/O card using less than 64 octet locations. Reads and writes to internal registers and buffer memory are performed by I/O accesses. Attribute memory (256 octets) is provided for the CIS table which is located in external memory. Common memory is not used. The following describes specific features of various pins: HA[9:0] Decoding of the system address space is performed by the HCEx-. During I/O accesses HA[5:0] decode the register. HA[9:6] are ignored when the internal HAMASK register is set to the defaults used by the standard firmware. During attribute memory accesses HA[9:1] are used. HD[15:0] The host interface is primarily designed for word accesses, although all byte access modes are fully supported. See HCE1-, HCE2- for a further description. Note that attribute memory is specified for and operates with even bytes accesses only. HCE1-, HCE2The PC Card cycle type and width are controlled with the CE signals. Word and Byte wide accesses are supported, using the combinations of HCE1-, HCE2-, and HA0 as specified in the PC Card standard.
17
Preliminary - HFA3841
buffer access path) will result in the pre-read data becoming invalidated. * If another read cycle has invalidated the pre-read, then a memory arbitration delay will occur on the next buffer access path read cycle. HIREQImmediately after reset, the HIREQ- signal serves as the RDY/BSY (per the PC Card standard). Once the HFA3841 firmware initialization procedure is complete, HIREQ- is configured to operate as the interrupt to the PC Card socket controller. Both Level Mode and Pulse Mode interrupts are supported. By default, Level mode interrupts are used, so the interrupt source must be specifically acknowledged or disabled before the interrupt will be removed. HRESET When reset is removed, the CIS table is initialized and, once complete, HIREQ- is set high (HIREQ- acts as RDY/BSY from reset and is set high to indicate the card is ready for use). The CIS table resides in Flash memory and is copied to RAM during firmware initialization. The host system can then initialize the card by reading the CIS information and writing to the configuration register. MEMORY MAPPED REGISTERS IN DATA RAM (MM) * 1 to 1 correspondence. * Requires memory arbitration, since registers are actually locations in HFA3841 memory. * Attribute memory access is mapped into RAM as Baseaddress + 0x400. * AUX port provides host access to any location in HFA3841 RAM (reserved). BUFFER ACCESS PATH (BAP) * No 1 to 1 correspondence between register address and memory address (due to indirect access through buffer address pointer registers). * Auto increment of pointer registers after each access. * Require memory arbitration since buffers are located in HFA3841 memory. * Buffer access may incur additional delay for Hardware Buffer Chaining.
I/O OFFSET 00 02 04 06 08 0A 0C 0E 10 20 22 24 18 1C 36 1A 1E 38 30 32 34 14 28 2A 2C 3A 3C 3E NAME Command Param0 Param1 Param2 Status Resp0 Resp1 Resp2 InfoFID RxFID AllocFID TxComplFID BAP Select0 BAP Offset0 BAP Data0 BAP Select1 BAP Offset1 BAP Data1 EvStat IntEn EvAck Control SwSupport0 SwSupport1 SwSupport2 AuxBase AuxOffset AuxData TYPE MM MM MM MM MM MM MM MM MM MM MM MM MM MM BAP MM MM BAP HW HW HW MM MM MM MM HW HW (reserved)
ISA PnP
The HFA3841 can be connected to the ISA bus and operate in a Plug and Play environment with an additional chip such as the Fujitsu MB86703, Texas Instruments TL16PNP200A, or Fairchild Semiconductor NM95MS15. See the Application Note AN9874, "ISA Plug and Play with the HFA3841" for more details.
Register Interface
The logical view of the HFA3841 from the host is a block of 32 word wide registers. These appear in IO space starting at the base address determined by the socket controller. There are three types of registers. HARDWARE REGISTERS (HW) * 1 to 1 correspondence between addresses and registers. * No memory arbitration delay, data transfer directly to/from registers. * AUX base and offset are write-only, to set up access through AUX data port. * Note: All register cycles, including hardware registers, incur a short wait state on the PC Card bus to insure the host cycle is synchronized with the HFA3841's internal MCLK.
18
Preliminary - HFA3841
Buffer Access Paths
The HFA3841 has two independent buffer access paths, which permits concurrent read and write transfers. The firmware provides dynamic memory allocation between Transmit and Receive, allowing efficient memory utilization. On-the-fly allocation of (128-byte) memory blocks as needed for reception wastes minimal space when receiving fragments. The HFA3841 hides management of free memory from the driver, and allows fast response and minimum data copying for low latency. The firmware provides direct access to TX and RX buffers based on Frame ID (FID). This facilitates Power Management queuing, and allows dynamic fragmentation and defragmentation by controller. Simple Allocate/Deallocate commands insure low host CPU overhead for memory management. Hardware buffer chaining provides high performance while reading and writing buffers. Data is transferred between the host driver and the HFA3841 by writing or reading a single register location (The Buffer Access Path, or BAP). Each access increments the address in the buffer memory. Internally, the firmware allocates blocks of memory as needed to provide the requested buffer size. These blocks may not be contiguous, but the firmware builds a linked list of pointers between them. When the host driver is transferring data through a buffer access path and reaches the end of a physical memory block, hardware in the host interface follows the linked list so that the buffer access path points to the beginning of the next memory block. This process is completely transparent to the host driver, which simply writes or reads all buffer data to the same register. If the host driver attempts to access beyond the end of the allocated buffer, subsequent writes are ignored, and reads will be undefined.
FID
BUFFER DESCRIPTOR ACCESS (FIRMWARE)
BUFFER MEMORY VIRTUAL FRAME BUFFER
ALLOCATE/ DEALLOCATE REQUEST OFFSET CENTER HOST BUS DATA PORT PRE-READ/ POST-WRITE
BLOCK A OFFSET
STATUS
HEADER
D DATA
FIGURE 15. BLOCK DIAGRAM OF A BUFFER ACCESS PATH
19
Preliminary - HFA3841 PHY Interface
The HFA3841 is intended to support the PRISM family of Baseband processors with no additional components. This family currently includes the HFA3860B and HFA3861 DSSS baseband processors and the other ICs in the PRISM WLAN chip set. (Other baseband processors may be supported with custom firmware. See your sales representative for more information). The HFA3841 interfaces to the HFA386X baseband processors through two serial interfaces. The Modem Management Interface (MMI) is used to read and write internal registers in the baseband processor and access per-packet PLCP information. The Modem Data Interface (MDI) provides the receive and transmit data paths which transfer the actual MPDU data. The PRISM II baseband processor mode works as follows: The Control Port consists of 4 signals: SD (serial data), SCLK (serial clock), R/W (read/write) and CS_BAR (activelow chip select). Control Port signaling for read and write operations is illustrated in Figures 16 and 17 respectively. Detailed timing relationships appear in Figure 18 and timing specifications are contained in Table 1. The BBP always uses the rising edge when clocking data on the Control Port. This means that when the BBP is receiving data it uses the rising edge of clock to sample; when driving data, transitions occur on the rising edge. Address bits 6 through 1 are significant for selecting configuration registers. Address bits 7 and 0 are unused. See the BBP Programming section for register addresses and suggested values. For read operations, the rising edge of R/W must occur after the 7th but prior to the 8th rising edge of SCLK. This ensures that the first data bit is clocked out of the BBP prior to the edge used to clock it into the MAC. For more detailed information on the Control Port and BBP register programming see the HFA386x data sheets.
Serial Control Port (MMI)
The HFA3841 has a serial port that is used to program the baseband processor. There are individual chip selects and shared clock and data lines. The MMI is used to program the registers and functionality of the PHY baseband processor. PHY BASEBAND PROCESSOR The PHY baseband processor is programmed by HFA3841 firmware.
FIRST ADDRESS BIT 7 SCLK 6 5 4 3 2 1 0
FIRST DATABIT OUT 7 6 5 4 3 2 1 0
SD
7 MSB
6
5
4
3
2
1
07 7 6 6 5 MSB
4
3
2
1
0 LSB
ADDRESS IN
DATA OUT
R/W CS
FIGURE 16. PRISM II BASEBAND PROCESSOR CONTROL PORT READ TIMING
7 SCLK
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SD
7 MSB
6
5
4
3
2
1
0
7 MSB
6
5
4 DATA IN
3
2
1
0 LSB
ADDRESS IN
R/W
CS
FIGURE 17. PRISM II BASEBAND PROCESSOR SERIAL CONTROL PORT WRITE TIMING
20
Preliminary - HFA3841
tSCP tSCW tSCW
SCLK tSCS SDI, R/W, SD, CS tSCD SD (AS OUTPUT) tSCH
R/W SD tSCED tSCED
FIGURE 18. BBP CONTROL PORT SIGNAL TIMING
TABLE 1. BBP CONTROL PORT AC ELECTRICAL SPECIFICATIONS PARAMETER SCLK Clock Period SCLK Width Hi or Low Setup to SCLK + Edge (SD, SDI, R/W, CS) Hold Time from SCLK + Edge (SD, SDI, R/W, CS) SD Out Delay from SCLK + Edge SD Out Enable/Disable from R/W SYMBOL tSCP tSCW tSCS tSCH tSCD tSCED MIN 90 20 30 MAX UNITS
LE_RF
SYNTHCLK
ns ns ns FIGURE 19. SYNTHESIZER DATA FORMAT
SYNTHDATA D23 D22 D21 D20 D1 D0
0
-
ns
PHY Data Interface (MDI)
The HFA3841 has a dedicated serial port to provide the data interface to the baseband processor. This is referred to as the Modem Data Interface (MDI). The MDI operates on the data being transferred to and from the baseband on a word by word basis. There are no FIFOs needed, since the firmware is able to control the protocol in real time. The MDI performs the following functions: * Serial to parallel conversion of received data from the baseband, with synchronization between the incoming RX clock to the internal HFA3841 clock. * Generating CRCs (HEC and FCS) from the received data stream to verify correct reception. * Decrypt the received data when WEP is enabled. * Parallel to serial conversion of transmit data, with the serial timing synchronized with the TX clock. * Insertion of the CRCs (HEC and FCS) at the appropriate point during transmission. * Encrypt the transmitted data when WEP is enabled. The receive data path uses RX_RDY, RXC, RXD. The transmit data path uses TX_RDY, TXC, TXD and the CCA input to determine (under the IEEE802.11 protocol) whether to transmit.
-
30
ns
-
15
ns
SYNTHESIZER For the PRISM II, the synthesizer is programmed by firmware using different pins than the MMI. The HFA3841 will exchange data with the baseband during transmit and receive operations over the MMI interface. If the MMI interface was connected to the front end chips, the transitions on SCLK and SD could couple noise into them. The synthesizer serial bus consists of SYNTHDATA, SYNTHCLK, LE_IF and LE_RF. SYNTHDATA is on pin PK2, SYNTHCLK is on PK1, LE_IF is the enable for the HFA3783 Quad IF chip, and LE_RF is the enable for the HFA3683 synthesizer. Data is provided on SYNTHDATA and clock on SYNTHCLK. The data is updated the falling edge of SYNTHCLK and expected to be latched into the synthesizer on the rising edge. The enable signal LE_RF is asserted while data is clocked out.
21
Preliminary - HFA3841
In transmit mode, the HFA386X is used in the mode where it generates the PLCP header internally and only the MPDU is passed from HFA3841. In receive, the HFA386X is used in the mode where it passes the PLCP header and the MPDU to the HFA3841. BBP Packet Reception There are 4 signals associated with the BBP Receive Port: RX_PE (receive enable), MDRDY (receive ready), RXD (receive data), and RXCLK (receive clock). These connect to the HFA3841 on pins PL1, PK5, RXD, and RXC, respectively. The receive demodulator in the BBP is activated via RX_PE. When RX_PE goes active the demodulator scrutinizes I and Q for packet activity. When a packet arrives at a valid signal level the demodulator acquires and tracks the incoming signal. It then sifts through the demodulator data for the Start Frame Delimiter (SFD). Normally, MDRDY is programmed to go active after SFD is detected. This signals the HFA3841, allowing it to pick off the needed header fields from the realtime demodulated bitstream rather than having to read these fields through the BBP Control Port. Assuming all is well with the header, the BBP decodes the signal field in the header and switches to the appropriate data rate. If the signal field is not recognized, or the CRC16 is in error, then MDRDY will go inactive shortly after CRC16 and the demodulator will return to acquisition mode looking for another packet. If all is well with the header, and after the demodulator has switched to the appropriate data rate, then the demodulator will continue to provide data to the HFA3841 indefinitely. Receive Port exchange details are depicted in Figure 20. Detailed timing is related in Figure 21 and Table 2. For more detailed information concerning BBP packet reception see the HFA386x data sheets.
RXC
RX_PE
HEADER FIELDS DATA
MDRDY
PROCESSING PREAMBLE/HEADER
LSB RXD
DATA PACKET
MSB
FIGURE 20. BBP RECEIVE PORT TIMING
tRLP RX_PE
tRD3 tREH IIN , QIN tRD2
MDRDY
tRCP
RXC tRCD
RXD
tCCA tRDS tRDI tRDD
tRCD
CCA, RSSI
FIGURE 21. BBP RECEIVE PORT SIGNAL TIMING NOTE: RXD, MDRDY is output two MCLK after RXC rising to provide hold time. RSSI output on TEST (5:0).
22
Preliminary - HFA3841
TABLE 2. BBP RECEIVE PORT AC ELECTRICAL SPECIFICATIONS PARAMETER RX_PE Inactive Width RXC Period (11MBps Mode) RXC Width Hi or Low (11MBps Mode) RXC to RXD MD_RDY to 1st RXC RXD to 1st RXC Setup RXD to RXC RXC to RX_PE Inactive (1MBps) RXC to RX_PE Inactive (2MBps) RXC to RX_PE Inactive (5.5MBps) RXC to RX_PE Inactive (11MBps) RX_PE inactive to MD_RDY Inactive Last Chip of SFD in to MD_RDY Active RX Delay RX_PE to CCA Valid RX_PE to RSSI Valid NOTES: 13. RX_PE must be inactive at least 3 MCLKs before going active to start a new CCA or acquisition. 14. MD_RDY programmed to go active after SFD detect (measured from IIN, QIN). 15. RX_PE active to inactive delay to prevent next RXC. 16. Assumes RX_PE inactive after last RXC. 17. MD_RDY programmed to go active at MPDU start. Measured from first chip of first MPDU symbol at IIN, QIN to MD_RDY active. 18. CCA and RSSI are measured once during the first 10s interval following RX_PE going active. RX_PE must be pulsed to initiate a new measurement. RSSI may be read via serial port or from Test Bus. TXC to TX_PE Inactive (11MBps) TXRDY Inactive To Last Chip of MPDU Out TXD Modulation Extension NOTES: 19. IOUT/QOUT are modulated before first valid chip of preamble is output to provide ramp up time for RF/IF circuits. 20. TX_PE must be inactive before going active to generate a new packet. 21. IOUT/QOUT are modulated after last chip of valid data to provide ramp down time for RF/IF circuits. 22. Delay from TXC to inactive edge of TXPE to prevent next TXC. Because TXPE asynchronously stops TXC, TXPE going inactive within 40ns of TXC will cause TXC minimum hi time to be less than 40ns. tPEH tRI 0 65 ns (Note 22) tCCA tCCA SYMBOL tRLP tRCP tRCD tRDD tRD1 tRD! tRDS tREH tREH tREH tREH tRD2 tRD3 MIN 70 77 MAX UNITS ns (Note 13) ns
31
-
ns
20 940 940 31 0
60 925
ns ns (Note 14) ns ns ns (Note 15)
signals the BBP with the signal TX_PE. The BBP forms the preamble and header and then signals the MAC to begin transferring data with the signal TXRDY. This sequence is illustrated in Figure 22 with detailed signal timing shown in Figure 23 and specified delays contained in Table 3. Note that if the MAC deactivates TX_PE too early it may cut off modulation of the final symbol. For this reason, when TX_PE is de-asserted the BBP will hold TXRDY active until the last symbol containing data is modulated. This is important for power sequencing and is discussed in more detail in that section. For more detailed information concerning BBP packet transmission see the HFA3861 data sheet.
TABLE 3. BBP TRANSMIT PORT AC ELECTRICAL SPECIFICATIONS PARAMETER TX_PE to IOUT/QOUT (1st Valid Chip) TX_PE Inactive Width SYMBOL tD1 tTLP tTCD tRC tTDS tTDH tPEH tPEH tPEH MIN 2.18 MAX 2.3 UNITS s (Note 19) s (Note 20) ns ns
0
380
ns (Note 15)
2.22 40 260
-
0
140
ns (Note 15) TXC Width Hi or Low
0
50
ns (Note 15)
TXRDY Active to 1st TX_CLK Hi Setup TXD to TXC Hi Hold TXD to TXC Hi
5
30
ns (Note 16) s (Note 14) s (Note 17) s (Note 18) s (Note 18)
30 0 0
965
ns ns ns (Note 22)
2.77
2.86
TXC to TX_PE Inactive (1MBps) TXC to TX_PE Inactive (2MBps) TXC to TX_PE Inactive (5.5MBps)
2.77 -
2.86 10 10
0
420
ns (Note 22)
0
160
ns (Note 22)
-20
20
ns
tME
2
-
s (Note 21)
BBP Packet Transmission There are 4 signals associated with the BBP Transmit Port: TX_PE (transmit enable), TXRDY (transmit ready), TXD (transmit data), and TXCLK (transmit clock). These connect to the HFA3841 on PL0, PL7, TXD, and TXC, respectively. State machines within the BBP control packet transmission and reception. In the case of a transmission, the MAC 23
Preliminary - HFA3841
TXC
TX_PE
FIRST DATA BIT SAMPLED
LAST DATA BIT SAMPLED
TXD
LSB
DATA PACKET
MSB DEASSERTED WHEN LAST CHIP OF MPDU CLEARS MOD PATH OF 3861
TXRDY
NOTE: Preamble/Header and Data is transmitted LSB first. TXD shown generated from rising edge of TXC. FIGURE 22. BBP TRANSMIT PORT TIMING
tTLP TX_PE tDI IOUT, QOUT tRI TXRDY tRC TXC TXD tTDH tTDS tTCD t TCD tPEH tME
FIGURE 23. BBP TRANSMIT PORT SIGNAL TIMING
Power Sequencing
The HFA3841 provides a number of firmware controlled port pins that are used for controlling the power sequencing and other functions in the front end components of the PHY. Packet transmission requires precise control of the radio. Ideally, energy at the antenna ceases after the last symbol of information has been transmitted. Additionally, the transmit/receive switch must be controlled properly to protect the receiver. It's also important to apply appropriate modulation to the PA while it's active. Signaling sequences for the beginning and end of normal transmissions are illustrated in Figure 24. Table 4 lists applicable delays. A transmission begins with PE2 as shown in Figure 24. Next, the transmit/receive switch is configured for transmission via the differential pair TR_SW and TR_SW_BAR. This is followed by TX_PE which activates the transmit state machine in the BBP. Lastly, PA_PE activates the PA. Delays for these signals related to the initiation of transmission are referenced to PE2. Immediately after the final data bit has been clocked out of the HFA3841, TX_PE is de-asserted. The HFA3841 then waits for TXRDY to go inactive, signaling that the BBP has modulated the final information-rich symbol. It then immediately de-asserts PA_PE followed by placing the transmit/receive switch in the receive position and ending with PE2 going high. Delays for these signals related to the termination of transmission are referenced to the rising edge of PE2.
24
Preliminary - HFA3841
PE1
PE2
TR_SW TR_SW_BAR
tD1
tD5
TX_PE tD2
TX_RDY
PA_PE tD3 tD4
FIGURE 24. TRANSMIT CONTROL SIGNAL SEQUENCING
TABLE 4. TRANSMIT CONTROL TIMING SPECIFICATIONS PARAMETER PE2 to TR Switch PE2 to BBP TX_PE PE2 to PA_PE PA_PE to PE2 TR Switch to PE2 SYMBOL tD1 tD2 tD3 tD4 tD5 DELAY 2 TBD 3 3 2 TOLERANCE UNITS 0.1 0.1 0.1 0.1 0.1 s s s s s
TABLE 5. POWER ENABLE STATES PE1 Power Down State Receive State Transmit State PLL Active State PLL Disable State 0 1 1 0 X PE2 0 1 0 1 X PLL_PE 1 1 1 1 0
PE1 and PE2 encoding details are found in Table 5. Note that during normal receive and transmit operation that PE1 is static and PE2 toggles for receive and transmit states.
NOTE: PLL_PE is controlled via the serial interface, and can be used to disable the internal synthesizer, the actual synthesizer control is an AND function of PLL_PE, and a result of the OR function of PE1 and PE2. PE1 and PE2 will directly control the power enable functionality of the LO buffer(s)/phase shifter.
25
Preliminary - HFA3841 Master Clock
Prescaler
The HFA3841 contains a clock prescaler to provide flexibility in the choice of clock input frequencies. For 11Mb/s operation, the internal master clock, MCLK, must be between 11MHz and 16MHz. The clock generator itself requires an input from the prescaler that is twice the desired MCLK frequency. Thus the lowest oscillator frequency that can be used for an 11MHz MCLK is 22MHz. The prescaler can divide by integers and 1/2 steps (IE 1, 1.5, 2, 2.5). Another way to look at it is that the divisor ratio between the external clock source and the internal MCLK may be integers between 2 and 14. Typically, the 44MHz baseband clock is used as the input, and the prescaler is set to divide by 2. Another useful configuration is to set the prescaler to divide by 1.5 (resulting in 44MHz /3) for an MCLK of 14.67MHz. The MD[15:8] pin values are sampled on the falling edge of HRESET or SRESET. These pins have internal 50K pulldown resistors. External pull-up resistors (typically 10k) are used for bits that should be read as high at reset. The table below summarizes the effect per pin.
TABLE 6. POR PINS AND FUNCTIONALITY PIN MD[8] MD[9] MD[10] MD[11] MD[12] MD[15:13] LATCH OUTPUT Reserved Nvdis MEM16 IDLE Reserved MD15/14/13 FW purposes Disable mapping of CS to NV (Flash) External memory (RAM and Flash) is 16 bits wide See below FUNCTIONALITY
Off Chip
If an off chip oscillator source is used, it should be connected to the XTALI pin. Insure that the signal amplitude meets CMOS levels at the XTALI pin.
Oscillator
The XTALI and XTALO pins provide an on-chip oscillator function to generate the master clock. For a standard pierce oscillator, the crystal is connected between XTALI and XTALO. Two capacitors, typically 15pF each, are connected from each pin to ground. The crystal should be a fundamental mode, specified under parallel resonance conditions. The load capacitance seen by the crystal will be approximately 2pF more than the series combination of C1 and C2 plus stray capacitance. After power on, the crystal will require time to stabilize before normal operation can commence. Insure that reset remains asserted for enough time for the crystal oscillator to stabilize.
C1
MD[11], IDLE, has no equivalent functionality in any control register. When asserted at reset, it will inhibit firmware execution. This is used to allow the initial download of firmware in "Genesis Mode". See the Hardware Reference Manual for more details. The latch is cleared when the Software Reset, SRESET, COR(7) is active.
References
For Intersil documents available on the internet, see web site http://www.intersil.com/ Intersil AnswerFAX (321) 724-7800. [1] IEEE Std 802.11-1999 Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specification. [2] HFA3860B Data Sheet, Direct Sequence Spread Spectrum Baseband Processor, Intersil Corporation, AnswerFAX Doc. No. 4594. [3] HFA3861 Data Sheet, Direct Sequence Spread Spectrum Baseband Processor, Intersil Corporation, AnswerFAX Doc. No. 4699. [4] HFA3783 Data Sheet, Quad IF, Intersil Corporation, AnswerFAX Doc. No. 4633.
XTALI X1
C2 XTALO
[5] HFA3683 Data Sheet, Direct Sequence Spread Spectrum Baseband Processor, Intersil Corporation, AnswerFAX Doc. No. 4634. [6] PC Card Standard 1996, PCMCIA/JEIDA. [7] AN9874 Application Note, Intersil Corporation, "ISA Plug and Play with the HFA3841".
FIGURE 25. POWER ON RESET CONFIGURATION
Power On Reset Configuration
Power On Reset is issued to the HFA3841 with the HRESET pin or via the soft reset bit, SRESET, in the Configuration Option Register (COR, bit 7). HRESET originates from the HOST system which applies HRESET for at least 0.01ms after VCC has reached 90% of its end value (see PC-Card standard, Vol. 2, Ch. 4.12.1).
[8] AN9844 Application Note, Intersil Corporation, "HFA3841 to PRISMII Connections", AnswerFAX Doc. No. 99844
26
Preliminary - HFA3841 Thin Plastic Quad Flatpack Packages (LQFP)
D D1 -D-
Q128.14x20 (JEDEC MS-026BHB ISSUE C)
128 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE SYMBOL A A1 A2 INCHES MIN 0.002 0.054 0.007 0.007 0.862 0.783 0.626 0.547 0.018 128 0.0197 BSC MAX 0.062 0.005 0.057 0.010 0.009 0.870 0.791 0.634 0.555 0.029 MILLIMETERS MIN 0.05 1.35 0.17 0.17 21.90 19.90 15.90 13.90 0.45 128 0.50 BSC MAX 1.60 0.15 1.45 0.27 0.23 22.10 20.10 16.10 14.10 0.75 NOTES 6 3 4, 5 3 4, 5 7 Rev. 0 7/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- .
0.13 A-B S 0.005 M C DS b b1 0.09/0.16 0.004/0.006 BASE METAL WITH PLATING
-AE E1
-B-
b b1 D D1 E
e
PIN 1 SEATING A PLANE 0.08 0.003 -C-
E1 L N e
-H-
4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 7. "N" is the number of terminal positions.
11o-13o 0.020 0.008 MIN 0o MIN GAGE PLANE L 0o-7o 0.25 0.010 11o-13o A2 A1
0.09/0.20 0.004/0.008
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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